- 174740 - Engineer Circuit Design 5 (UVM) - CA
- CA-S.Cali-Los Angeles/Orange Counties
- Redondo Beach
- Up to $85.00 DOE
- 1 year
Northrop Grumman Aerospace Systems is seeking an Engineer Circuit Design 5 based in Redondo Beach, CA. This person will join the Digital Products Department. The ideal candidate is an Engineer experienced in Modeling and Verification. This person will work on multi-million gate ASIC and FPGA developments in the areas of digital communications, signal processing, network routing, embedded processors and switching applications for air and space applications.
The responsibilities of this position include developing verification plans, architecting and implementing verification environments, writing and executing tests, and documenting verification results to support requirements selloff. Candidate must have digital verification expertise using advanced verification methodologies and techniques including constrained-random verification using System Verilog and OVM/UVM, assertions and functional coverage using PSL or SVA, and modeling using C/C++, System Verilog, or System C.
Bachelor's degree in a STEM discipline with a minimum 15 years of relevant experience.
Must have experience with Verification using System Verilog and OVM/UVM.
Mentor Questa simulator, VHDL or Verilog, PSL or SVA, C/C++, System C.
Bachelor's degree in a STEM discipline is required.
Lucas Medina at firstname.lastname@example.org
420 Culver Boulevard
Playa Del Rey, CA 90293
Phone: (310) 414-7800 x250 or (800) 927-9318 x250
Candidates responding to this posting must currently possess the eligibility to work in the United States. No third parties please.
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